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FINAL
AM28F010
1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s High performance -- 70 ns maximum access time s CMOS Low power consumption -- 30 mA maximum active current -- 100 A maximum standby current -- No data retention power consumption s Compatible with JEDEC-standard byte-wide 32-Pin EPROM pinouts -- 32-pin PDIP -- 32-pin PLCC -- 32-pin TSOP s 10,000 write/erase cycles minimum s Write and erase voltage 12.0 V 5% s Latch-up protected to 100 mA from -1 V to V CC +1 V s FlasheraseTM Electrical Bulk Chip-Erase -- One second typical chip-erase s FlashriteTM Programming -- 10 s typical byte-program -- Two seconds typical chip program s Command register architecture for microprocessor/microcontroller compatible write interface s On-chip address and data latches s Advanced CMOS flash memory technology -- Low cost single transistor memory cell s Automatic write/erase pulse stop timer
GENERAL DESCRIPTION
The AM28F010 is a 1 Megabit Flash memory organized as 128 Kbytes of 8 bits each. AMD's Flash memories offer the most cost-effective and reliable read/ write non-volatile random access memor y. The AM28F010 is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The AM28F010 is erased when shipped from the factory. The standard AM28F010 offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the AM28F010 has separate chip enable (CE#) and output enable (OE#) controls. AMD's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The AM28F010 uses a command register to manage this functionality, while maintaining a JEDEC Flash Standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. AMD's Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The AMD cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The AM28F010 uses a 12.0 V 5% V PP high voltage input to perform the Flasherase and Flashrite algorithms. The highest degree of latch-up protection is achieved with AMD's proprietary non-epi process. Latch-up protection is provided for stresses up to 100 milliamps on address and data pins from -1 V to V CC +1 V. The AM28F010 is byte programmable using 10 ms programming pulses in accordance with AMD's Flashrite programming algorithm. The typical room temperature programming time of the AM28F010 is two seconds. The entire chip is bulk erased using 10 ms erase pulses according to AMD's Flasherase alrogithm. Typical erasure at room temperature is accomplished in less than one second. The windowed package and the 15-20
Publication# 11559 Rev: H Amendment/+2 Issue Date: January 1998
minutes required for EPROM erasure using ultra-violet light are eliminated. Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the AM28F010 is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the ris-
ing edge of WE# or CE# whichever occurs first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal. AMD's Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The AM28F010 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
BLOCK DIAGRAM
DQ0-DQ7 VCC VSS VPP Erase Voltage Switch To Array WE# State Control Command Register CE# OE# Program Voltage Switch Chip Enable Output Enable Logic Input/Output Buffers
Data Latch
Y-Decoder Low V CC Detector Address Latch Program/Erase Pulse Timer
Y-Gating
X-Decoder
1,048,576 Bit Cell Matrix
A0-A16
11559H-1
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options (VCC = 5.0 V 10%) Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns) -70 70 70 35 -90 90 90 35 AM28F010 -120 120 120 50 -150 150 150 55 -200 200 200 55
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AM28F010
CONNECTION DIAGRAMS
PDIP PLCC
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
A16
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
WE# (W#) NC A14 A13 A8 A9 A11 OE# (G#) A10 CE# (E#) DQ7 DQ6 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
43
2
1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE# (G#) A10 CE# (E#) DQ7
14 15 16 17 18 19 20 VSS DQ3 DQ1 DQ2 DQ4 DQ5 DQ6
DQ5 DQ4 DQ3
11559H-2
VCC
A12 A15
1
32
VCC
WE# (W#) NC
NC
11559H-3
Note: Pin 1 is marked for orientation.
AM28F010
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CONNECTION DIAGRAMS (continued)
TSOP
A11 A9 A8 A13 A14 NC WE# VCC NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3
32-Pin TSOP--Standard Pinout
OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 A14 NC WE# VCC NC A16 A15 A12 A7 A6 A5 A4
11559H-4
32-Pin TSOP--Reverse Pinout
LOGIC SYMBOL
17 A0-A16 DQ0-DQ7 CE# (E#) OE# (G#) WE# (W#) 8
11559H-5
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AM28F010
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM28F010 -70 J C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) E = Extended (-55C to +125C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION AM28F010 1 Megabit (128 K x 8-Bit) CMOS Flash Memory
Valid Combinations AM28F010-70 AM28F010-90 AM28F010-120 AM28F010-150 AM28F010-200 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
AM28F010
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PIN DESCRIPTION A0-A16 Address Inputs for memory locations. Internal latches
hold addresses during write cycles.
VCC
Power supply for device operation. (5.0 V 5% or 10%)
VPP
Program voltage input. V PP must be at high voltage in order to write to the command register. The command register controls all functions required to alter the memory array contents. Memory contents cannot be altered when VPP VCC +2 V.
CE# (E#)
Chip Enable active low input activates the chip's control logic and input buffers. Chip Enable high will deselect the device and operates the chip in stand-by mode.
DQ0-DQ7
Data Inputs during memor y write cycles. Internal latches hold data during write cycles. Data Outputs during memory read cycles.
VSS
Ground
WE# (W#)
Write Enable active low input controls the write function of the command register to the memory array. The target address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writing to the device.
NC
No Connect-corresponding pin is not connected internally to the die.
OE# (G#)
Output Enable active low input gates the outputs of the device through the data buffers during memory read cycles. Output Enable is high dur ing command sequencing and program/erase operations.
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AM28F010
BASIC PRINCIPLES
The device uses 100% TTL-level control inputs to manage the command register. Erase and reprogramming operations use a fixed 12.0 V 5% high voltage input. formation must be supplied with the Erase-verify command. This command verifies the margin and outputs the addressed byte in order to compare the a rray da t a w it h F F h d a t a (B yte e ra se d ). After successful data verification the Erase-verify command is written again with new address information. Each byte of the array is sequentially verified in this manner. If data of the addressed location is not verified, the Erase sequence is repeated until the entire array is successfully verified or the sequence is repeated 1000 times. Flashrite Programming Sequence A three step command sequence (a two-cycle Program command and one cycle Verify command) is required to program a byte of the Flash array. Refer to the Flashrite Algorithm. 1. Program Setup: Write the Setup Program command to the command register. 2. Program: Write the Program command to the command register with the appropriate Address and Data. The system software routines must now timeout the program pulse width (10 s) prior to issuing the Program-verify command. An integrated stop timer prevents any possibility of overprogramming. 3. Program-Verify: Write the Program-verify command to the command register. This command terminates the programming operation. In addition, this command verifies the margin and outputs the byte just programmed in order to compare the array data with the original data programmed. After successful data verification, the programming sequence is initiated again for the next byte address to be programmed. If data is not verified successfully, the Program sequence is repeated until a successful comparison is verified or the sequence is repeated 25 times.
Read Only Memory
Without high V PP voltage, the device functions as a read only memor y and operates like a standard EPROM. The control inputs still manage traditional read, standby, output disable, and Auto select modes.
Command Register
The command register is enabled only when high voltage is applied to the V PP pin. The erase and reprogramming operations are only accessed via the register. In addition, two-cycle commands are required for erase and reprogramming operations. The traditional read, standby, output disable, and Auto select modes are available via the register. The device's command register is written using standard microprocessor write timings. The register controls an internal state machine that manages all device operations. For system design simplification, the device is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occur first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.
Overview of Erase/Program Operations
FlasheraseTM Sequence A multiple step command sequence is required to erase the Flash device (a two-cycle Erase command and repeated one cycle verify commands).
Note: The Flash memory array must be completely programmed to 0's prior to erasure. Refer to the FlashriteTM Programming Algorithm.
1. Erase Setup: Write the Setup Erase command to the command register. 2. Erase: Write the Erase command (same as Setup Erase command) to the command register again. The second command initiates the erase operation. The system software routines must now time-out the erase pulse width (10 ms) prior to issuing the Erase-verify command. An integrated stop timer prevents any possibility of overerasure. 3. Erase-Verify: Write the Erase-verify command to the command register. This command terminates the erase operation. After the erase operation, each byte of the array must be verified. Address in-
Data Protection
The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. The device powers up in its read only state. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC powerup and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during V CC power-up and power-down, the device locks out write cycles for
AM28F010
7
V CC < V LKO (see DC Characteristics section for voltages). When VCC < VLKO, the command register is disabled, all inter nal program/erase circuits are disabled, and the device resets to the read mode. The device ignores all writes until V CC > VLKO. The user must ensure that the control pins are in the correct logic state when VCC > VLKO to prevent uninitentional writes.
Logical Inhibit
Writing is inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE# = CE# = VIL and OE# = VIH will not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
Write Pulse "Glitch" Protection
Noise pulses of less than 10 ns (typical) on OE#, CE# or WE# will not initiate a write cycle.
FUNCTIONAL DESCRIPTION Description of User Modes
Table 1.
Operation Read Standby Output Disable Read-Only Auto-Select Manufacturer Code (Note 2) Auto-Select Device Code (Note 2) Read Standby (Note 5) Read/Write Output Disable Write
AM28F010 Device Bus Operations
CE# (E#) VIL VIH VIL VIL VIL VIL VIH VIL VIL VPP OE# (G#) WE# (W#) (Note 1) VIL X VIH VIL VIL VIL X VIH VIH X X VIH VIH VIH VIH X VIH VIL VPPL VPPL VPPL VPPL VPPL VPPH VPPH VPPH VPPH A0 A0 X X VIL VIH A0 X X A0 A9 A9 X X VID (Note 3) VID (Note 3) A9 X X A9 I/O DOUT HIGH Z HIGH Z CODE (01h) CODE (A7h) DOUT (Note 4) HIGH Z HIGH Z DIN (Note 6)
Legend: X = Don't care, where Don't Care is either V IL or VIH levels. VPPL = V PP VCC + 2 V. See DC Characteristics for voltage levels of V PPH. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9). Notes: 1. VPPL may be grounded, connected with a resistor to ground, or < VCC + 2.0 V. VPPH is the programming voltage specified for the device. Refer to the DC characteristics. When V PP = VPPL, memory contents can be read but not written or erased. 2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2. 3. 11.5 < V ID < 13.0 V. Minimum V ID rise time and fall time (between 0 and VID voltages) is 500 ns. 4. Read operation with V PP = VPPH may access array data or the Auto select codes. 5. With VPP at high voltage, the standby current is ICC + IPP (standby). 6. Refer to Table 3 for valid DIN during a write operation. 7. All inputs are Don't Care unless otherwise stated, where Don't Care is either VIL or VIH levels. In the Auto select mode all addresses except A9 and A0 must be held at VIL. 8. If V CC 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the AM28F010 has a V PP rise time and fall time specification of 500 ns minimum.
8
AM28F010
READ ONLY MODE
When V PP is less than VCC + 2 V, the command register is inactive. The device can either read array or autoselect data, or be standby mode.
Auto Select
Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board. The Auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type. This mode is intended for the purpose of automatically matching the device to be programmed with its corresponding programming algor ith m. Th is mo de is f unc tio nal ove r t he en tir e temperature range of the device.
Read
The device functions as a read only memory when V PP < VCC + 2 V. The device has two control functions. Both must be satisfied in order to output data. CE# controls power to the device. This pin should be used for specific device selection. OE# controls the device outputs and should be used to gate data to the output pins if a device is selected. Address access time tACC is equal to the delay from stable addresses to valid output data. The chip enable access time tCE is the delay from stable addresses and stable CE# to valid data at the output pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable at least t ACC-tOE).
Programming In A PROM Programmer
To activate this mode, the programming equipment must force VID (11.5 V to 13.0 V) on address A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A 0 from VIL to VIH. All other address lines must be held at VIL , and VPP must be less than or equal to VCC + 2.0 V while using this Auto select mode. Byte 0 (A0 = VIL ) represents the manufacturer code and byte 1 (A0 = V IH) the device identifier code. For the device these two bytes are given in Table 2 below. All identifiers for manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit.
Standby Mode
The device has two standby modes. The CMOS standby mode (CE# input held at VCC 0.5 V), consumes less than 100 A of current. TTL standby mode (CE# is held at V IH) reduces the current requirements to less than 1mA. When in the standby mode the outputs are in a high impedance state, independent of the OE# input. If the device is deselected during erasure, programming, or program/erase verification, the device will draw active current until the operation is terminated.
Output Disable
Output from the device is disabled when OE# is at a logic high level. When disabled, output pins are in a high impedance state.
Table 2.
Type Manufacturer Code Device Code
AM28F010 Auto Select Code
A0 VIL VIH Code (HEX) 01 A7
AM28F010
9
ERASE, PROGRAM, AND READ MODE
When V PP is equal to 12.0 V 5%, the command register is active. All functions are available. That is, the device can program, erase, read array or autoselect data, or be standby mode. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Command Definitions
The contents of the command register default to 00h (Read Mode) in the absence of high voltage applied to the VPP pin. The device operates as a read only memory. High voltage on the VPP pin enables the command register. Device operations are selected by writing specific data codes into the command register. Table 3 defines these register commands.
Write Operations
High voltage must be applied to the V PP pin in order to activate the command register. Data written to the register serves as input to the internal state machine. The output of the state machine determines the operational function of the device. The command register does not occupy an addressable memory location. The register is a latch that stores the command, along with the address and data information needed to execute the command. The register is written by bringing WE# and CE# to VIL, while OE# is at VIH. Addresses are latched on the falling edge of WE#, while data is latched on the rising edge of the WE# pulse. Standard microprocessor write timings are used. The device requires the OE# pin to be VIH for write operations. This condition eliminates the possibility for bus contention during programming operations. In order to write, OE# must be VIH, and CE# and WE# must be VIL. If any pin is not in the correct state a write command will not be executed. Table 3.
Read Command
Memory contents can be accessed via the read command when V PP is high. To read from the device, write 00h into the command register. Standard microprocessor read cycles access data from the memory. The device will remain in the read mode until the command register contents are altered. The command register defaults to 00h (read mode) upon VPP power-up. The 00h (Read Mode) register default helps ensure that inadvertent alteration of the memory contents does not occur during the V PP power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
AM28F010 Command Definitions
First Bus Cycle Second Bus Cycle Data (Note 3) 00h/FFh 80h or 90h 20h A0h 40h C0h FFh Operation (Note 1) Read Read Write Read Write Read Write Address (Note 2) RA 00h/01h X X PA X X Data (Note 3) RD 01h/A7h 20h EVD PD PVD FFh
Command (Note 4) Read Memory Read Auto select Erase Setup/Erase Write Erase-Verify Program Setup/Program Program-Verify Reset
Operation (Note 1) Write Write Write Write Write Write Write
Address (Note 2) X X X EA X X X
Notes: 1. Bus operations are defined in Table 1. 2. RA = Address of the memory location to be read. EA = Address of the memory location to be read during erase-verify. PA = Address of the memory location to be programmed. X = Don't care. Addresses are latched on the falling edge of the WE# pulse. 3. RD = Data read from location RA during read operation. EVD = Data Read from location EA during erase-verify. PD = Data to be programmed at location PA. Data latched on the rising edge of WE#. PVD = Data read from location PA during program-verify. PA is latched on the Program command. 4. Refer to the appropriate section for algorithms and timing diagrams.
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AM28F010
FLASHERASE ERASE SEQUENCE Erase Setup
Erase Setup is the first of a two-cycle erase command. It is a command-only operation that stages the device for bulk chip erase. The array contents are not altered with this command. 20h is written to the command register in order to perform the Erase Setup operation. ated by writing A0h to the register. The byte address to be verified must be supplied with the command. Addresses are latched on the falling edge of the WE# pulse or CE# pulse, whichever occurs later. The rising edge of the WE# pulse terminates the erase operation.
Margin Verify
During the Erase-verify operation, the device applies an int er na lly g en erat ed ma rg in vo lta ge to th e addressed byte. Reading FFh from the addressed byte indicates that all bits in the byte are properly erased.
Erase
The second two-cycle erase command initiates the bulk erase operation. You must write the Erase command (20h) again to the register. The erase operation begins with the rising edge of the WE# pulse. The erase operation must be terminated by writing a new command (Erase-verify) to the register. This two step sequence of the Setup and Erase commands helps to ensure that memory contents are not accidentally erased. Also, chip erasure can only occur when high voltage is applied to the V PP pin and all control pins are in their proper state. In absence of this high voltage, memory contents cannot be altered. Refer to AC Erase Characteristics and Waveforms for specific timing parameters.
Verify Next Address
You must write the Erase-verify command with the appropriate address to the register prior to verification of each address. Each new address is latched on the falling edge of WE# or CE# pulse, whichever occurs later. The process continues for each byte in the memory array until a byte does not return FFh data or all the bytes in the array are accessed and verified. If an address is not verified to FFh data, the entire chip is erased again (refer to Erase Setup/Erase). Erase verification then resumes at the address that failed to verify. Erase is complete when all bytes in the array have been verified. The device is now ready to be programmed. At this point, the verification operation is terminated by writing a valid command (e.g. Program Setup) to the command register. Figure 1 and Table 4, the Flasherase electrical erase algorithm, illustrate how commands and bus operations are combined to perform electrical erasure. Refer to AC Erase Characteristics and Waveforms for specific timing parameters.
Note: The Flash memory device must be fully programmed to 00h data prior to erasure. This equalizes the charge on all memory cells ensuring reliable erasure.
Erase-Verify Command
The erase operation erases all bytes of the array in parallel. After the erase operation, all bytes must be sequentially verified. The Erase-verify operation is initi-
AM28F010
11
FLASHERASE ELECTRICAL ERASE ALGORITHM
This Flash memory device erases the entire array in parallel. The erase time depends on V PP, temperature, and number of erase/program cycles on the device. In general, reprogramming time increases as the number of erase/program cycles increases. The Flasherase electrical erase algorithm employs an interactive closed loop flow to simultaneously erase all bits in the array. Erasure begins with a read of the memory contents. The device is erased when shipped from the factory. Reading FFh data from the device would immediately be followed by executing the Flashrite programming algorithm with the appropriate data pattern. Should the device be currently programmed, data other than FFh will be returned from address locations. Follow the Flasherase algorithm. Uniform and reliable erasure is ensured by first programming all bits in the device to their charged state (Data = 00h). This is accomplished using the Flashr ite Programming algorithm. Erasure then continues with an initial erase operation. Erase verification (Data = FFh) begins at address 0000h and continues through the array to the la s t a d d r e s s, o r u n t i l d a t a o t h e r t h a n F F h i s encountered. If a byte fails to verify, the device is er as e d ag a in . W i th ea ch er as e o pe r at io n , a n increasing number of bytes verify to the erased state. Typically, devices are erased in less than 100 pulses (one second). Erase efficiency may be improved by storing the address of the last byte that fails to verify in a register. Following the next erase operation, verification may start at the stored address location. A total of 1000 erase pulses are allowed per reprogram cycle, which corresponds to approximately 10 seconds of cumulative erase time. The entire sequence of erase and byte verification is performed with high voltage applied to the VPP pin. Figure 1 illustrates the electrical erase algorithm.
Table 4.
Bus Operations
Flasherase Electrical Erase Algorithm
Comments Entire memory must = 00h before erasure (Note 3)
Command
Note: Use Flashrite programming algorithm (Figure 3) for programming.
Wait for VPP Ramp to VPPH (Note 1) Initialize: Addresses PLSCNT (Pulse count) Erase Setup Write Erase Standby Write Standby Read Standby Write Standby Reset Erase-Verify (Note 2) Data = 20h Duration of Erase Operation (tWHWH2) Address = Byte to Verify Data = A0h Stops Erase Operation Write Recovery Time before Read = 6 s Read byte to verify erasure Compare output to FFh Increment pulse count Data = FFh, reset the register for read operations Wait for VPP Ramp to VPPL (Note 1) Data = 20h
Standby
Notes: 1. See AC and DC Characteristics for values of V PP parameters. The V PP power supply can be hard-wired to the device or switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. 2. Erase Verify is performed only after chip erasure. A final read compare may be performed (optional) after the register is written with the read command. 3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.
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AM28F010
Start
Yes
Data = 00h
No Program All Bytes to 00h Apply V PPH Address = 00h PLSCNT = 0 Write Erase Setup Command Write Erase Command Time out 10 ms Write Erase Verify Time out 6 s Read Data from Device No No PLSCNT = 1000 Yes Apply VPPL Erase Error Increment PLSCNT Data = FFh Yes Last Address No Increment Address
Yes Write Reset Command Apply VPPL Erasure Completed
11559G-6
Figure 1.
Flasherase Electrical Erase Algorithm
AM28F010
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Section Addresses
A
B
C
D
E
F
G
CE#
OE#
WE#
Data
20h
20h
A0h
Data Out
VCC
VPP
11559G-7
A Bus Cycle Command Write 20h Erase Setup
B Write 20h
C Time-out N/A Erase (10 ms)
D Write A0h EraseVerify
E Time-out N/A Transition (6 s)
F Read Compare Data Erase Verification
G Standby N/A Proceed per Erase Algorithm
Function
Erase
Figure 2.
AC Waveforms For Erase Operations
Analysis of Erase Timing Waveform
Note: This analysis does not include the requirement to program the entire array to 00h data prior to erasure. Refer to the Flashrite Programming algorithm.
Time-Out
A software timing routine (10 ms duration) must be initiated on the rising edge of the WE# pulse of section B.
Erase Setup/Erase
This analysis illustrates the use of two-cycle erase commands (section A and B). The first erase command (20h) is a Setup command and does not affect the array data (section A). The second erase command (20h) initiates the erase operation (section B) on the rising edge of this WE# pulse. All bytes of the memory array are erased in parallel. No address information is required. The erase pulse occurs in section C.
Note: An integrated stop timer prevents any possibility of overerasure by limiting each time-out period of 10 ms.
Erase-Verify
Upon completion of the erase software timing routine, the microprocessor must write the Erase-verify command (A0h). This command terminates the erase operation on the rising edge of the WE# pulse (section D). The Erase-verify command also stages the device for data verification (section F). After each erase operation each byte must be verified. The byte address to be verified must be supplied with
14
AM28F010
the Erase-verify command (section D). Addresses are latched on the falling edge of the WE# pulse. Another software timing routine (6 s duration) must be executed to allow for generation of internal voltages for margin checking and read operation (section E). During Erase-verification (section F) each address that returns FFh data is successfully erased. Each address of the array is sequentially verified in this manner by repeating sections D thru F until the entire array is verified or an address fails to verify. Should an address
location fail to verify to FFh data, erase the device again. Repeat sections A thru F. Resume verification (section D) with the failed address. Each data change sequence allows the device to use up to 1,000 erase pulses to completely erase. Typically 100 erase pulses are required.
Note: All address locations must be programmed to 00h prior to erase. This equalizes the charge on all memory cells and ensures reliable erasure.
FLASHRITE PROGRAMMING SEQUENCE Program Setup
The device is programmed byte by byte. Bytes may be programmed sequentially or at random. Program Setup is the first of a two-cycle program command. It stages the device for byte programming. The Program Setup operation is performed by writing 40h to the command register. Program-verify operation stages the device for verification of the last byte programmed. Addresses were previously latched. No new information is required.
Margin Verify
During the Program-verify operation, the device applies an internally generated margin voltage to the addressed byte. A normal microprocessor read cycle outputs the data. A successful comparison between the programmed byte and the true data indicates that the byte was successfully programmed. The original programmed data should be stored for comparison. Programming then proceeds to the next desired byte location. Should the byte fail to verify, reprogram (refer to Program Setup/Program). Figure 3 and Table 5 indicate how instructions are combined with the bus operations to perform byte programming. Refer to AC Programming Characteristics and Waveforms for specific timing parameters.
Program
Only after the program Setup operation is completed will the next WE# pulse initiate the active programming operation. The appropriate address and data for programming must be available on the second WE# pulse. Addresses and data are internally latched on the falling and rising edge of the WE# pulse respectively. The rising edge of WE# also begins the programming operation. You must write the Program-verify command to terminate the programming operation. This two step sequence of the Setup and Program commands helps to ensure that memory contents are not accidentally written. Also, programming can only occur when high voltage is applied to the VPP pin and all control pins are in their proper state. In absence of this high voltage, memory contents cannot be programmed. Refer to AC Characteristics and Waveforms for specific timing parameters.
Flashrite Programming Algorithm
The device Flashrite Programming algorithm employs an interactive closed loop flow to program data byte by byte. Bytes may be programmed sequentially or at random. The Flashrite Programming algorithm uses 10 s programming pulses. Each operation is followed by a byte verification to determine when the addressed byte has been successfully programmed. The program algorithm allows for up to 25 programming operations per byte per reprogramming cycle. Most bytes verify after the first or second pulse. The entire sequence of programming and byte verification is performed with high voltage applied to the VPP pin. Figure 3 and Table 5 illustrate the programming algorithm.
Program Verify Command
Following each programming operation, the byte just programmed must be verified. Write C0h into the command register in order to initiate the Program-verify operation. The rising edge of this WE pulse terminates the programming operation. The
AM28F010
15
Start Apply VPPH PLSCNT = 0 Write Program Setup Command Write Program Command (A/D) Time out 10 s Write Program Verify Command Time out 6 s Read Data from Device No Verify Byte Yes Increment Address No Last Address Yes Write Reset Command Apply VPPL Programming Completed Apply VPPL Device Failed
11559G-8
No
Increment PLSCNT
PLSCNT = 25? Yes
Figure 3.
Flashrite Programming Algorithm
16
AM28F010
Table 5.
Bus Operations Standby Program Setup Write Program Standby Write Standby Read Standby Write Standby Reset
Flashrite Programming Algorithm
Comments Wait for VPP Ramp to VPPH (Note 1) Initialize Pulse counter Data = 40h Valid Address/Data Duration of Programming Operation (tWHWH1 )
Command
Program-Verify (Note 2)
Data = C0h Stops Program Operation Write Recovery Time before Read = 6 s Read Byte to Verify Programming Compare Data Output to Data Expected Data = FFh, resets the register for read operations. Wait for VPP Ramp to VPPL (Note 1)
Notes: 1. See AC and DC Characteristics for values of V PP parameters. The V PP power supply can be hard-wired to the device or switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. 2. Program Verify is performed only after byte programming. A final read/compare may be performed (optional) after the register is written with the read command.
AM28F010
17
Section Addresses
A
B
C
D
E
F
G
CE#
OE#
WE#
Data
20h
Data In
A0h
Data Out
VCC
VPP
11559G-9
A Bus Cycle Command Write 40h
B Write Program Address, Program Data Program Command Latch Address and Data
C Time-out N/A
D Write C0h (Stops Program)
E Time-out N/A
F Read Compare Data
G Standby N/A
Function
Program Setup
Program (10 s)
Program Verify
Transition (6 s)
Program Verification
Proceed per Programming Algorithm
Figure 4.
AC Waveforms for Programming Operations
ANALYSIS OF PROGRAM TIMING WAVEFORMS Program Setup/Program
Two-cycle write commands are required for program operations (section A and B). The first program command (40h) is a Setup command and does not affect the array data (section A). The second program command latches address and data required for programming on the falling and rising edge of WE# respectively (section B). The rising edge of this WE# pulse (section B) also initiates the programming pulse. The device is programmed on a byte by byte basis either sequentially or randomly. The program pulse occurs in section C.
Time-Out
A software timing routine (10 s duration) must be initiated on the rising edge of the WE# pulse of section B.
Note: An integrated stop timer prevents any possibility of overprogramming by limiting each time-out period of 10 s.
Program-Verify
Upon completion of the program timing routine, the microprocessor must write the program-verify command (C0h). This command terminates the programming operation on the rising edge of the WE# pulse (section D). The program-verify command also stages the device for data verification (section F). Another software timing
18
AM28F010
routine (6 s duration) must be executed to allow for generation of internal voltages for margin checking and read operations (section E). During program-verification (section F) each byte just programmed is read to compare array data with original program data. When successfully verified, the next desired address is programmed. Should a byte fail to verify, reprogram the byte (repeat section A thru F). Each data change sequence allows the device to use up to 25 program pulses per byte. Typically, bytes are verified within one or two pulses.
Parallel Device Erasure
Many applications will use more than one Flash memory device. Total erase time may be minimized by implementing a parallel erase algorithm. Flash memories may erase at different rates. Therefore each device must be verified separately. When a device is completely erased and verified use a masking code to prevent further erasure. The other devices will continue to erase until verified. The masking code applied could be the read command (00h).
Power-Up/Power-Down Sequence
The device powers-up in the Read only mode. Power supply sequencing is not required. Note that if V CC 1.0 Volt, the voltage difference between V PP and V CC should not exceed 10.0 Volts. Also, the device has VPP rise time and fall time specification of 500 ns minimum.
Algorithm Timing Delays
There are four different timing delays associated with the Flasherase and Flashrite algorithms: 1. The first delay is associated with the VPP rise-time when VPP first turns on. The capacitors on the VPP bus cause an RC ramp. After switching on the V PP, the delay required is proportional to the number of devices being erased and the 0.1 mF/device. VPP must reach its final value 100 ns before commands are executed. 2. The second delay time is the erase time pulse width (10 ms). A software timing routine should be run by the local microprocessor to time out the delay. The erase operation must be terminated at the conclusion of the timing routine or prior to executing any system interrupts that may occur during the erase operation. To ensure proper device operation, write the Erase-verify operation after each pulse. 3. A third delay time is required for each programming pulse width (10 ms). The programming algorithm is interactive and verifies each byte after a program pulse. The program operation must be terminated at the conclusion of the timing routine or prior to executing any system interrupts that may occur during the programming operation. 4. A fourth timing delay associated with both the Flasherase and Flashrite algorithms is the write recovery time (6 ms). During this time internal circuitry is changing voltage levels from the erase/ program level to those used for margin verify and read operations. An attempt to read the device during this period will result in possible false data (it may appear the device is not properly erased or programmed).
Reset Command
The Reset command initializes the Flash memory device to the Read mode. In addition, it also provides the user with a safe method to abort any device operation (including program or erase). The Reset command must be written two consecutive times after the setup Program command (40h). This will reset the device to the Read mode. Following any other Flash command write the Reset command once to the device. This will safely abort any previous operation and initialize the device to the Read mode. The Setup Program command (40h) is the only command that requires a two sequence reset cycle. The first Reset command is interpreted as program data. However, FFh data is considered null data during programming operations (memory cells are only programmed from a logical "1" to "0"). The second Reset command safely aborts the programming operation and resets the device to the Read mode. Memory contents are not altered in any case. This detailed information is for your reference. It may prove easier to always issue the Reset command two consecutive times. This eliminates the need to determine if you are in the setup Program state or not.
Programming In-System
Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board.
Note: Software timing routines should be written in machine language for each of the delays. Code written in machine language requires knowledge of the appropriate microprocessor clock speed in order to accurately time each delay.
AM28F010
19
Auto Select Command
AMD's Flash memories are designed for use in applications where the local CPU alters memory contents. Accordingly, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a generally desired system design practice. The device contains an Auto Select operation to supplement traditional PROM programming methodology. The operation is initiated by writing 80h or 90h into the command register. Following this command, a read cycle address 0000h retrieves the manufacturer code of 01h. A read cycle from address 0001h returns the device code. To terminate the operation, it is necessary to write another valid command, such as Reset (FFh), into the register.
20
AM28F010
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +125C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55C to + 125C Voltage with Respect To Ground All pins except A9 and V PP (Note 1) . -2.0 V to +7.0 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . -2.0 V to +7.0 V A9 (Note 2). . . . . . . . . . . . . . . . . . . . -2.0 V to +14.0 V VPP (Note 2). . . . . . . . . . . . . . . . . . . -2.0 V to +14.0 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may overshoot V SS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to V CC + 2.0V for periods up to 20ns. 2. Minimum DC input voltage on A9 and V PP pins is -0.5 V. During voltage transitions, A9 and V PP may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9 and V PP is +13.0 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA). . . . . . . . . . . .0C to +70C Industrial (I) Devices Ambient Temperature (TA). . . . . . . . . .-40C to +85C Extended (E) Devices Ambient Temperature (TA). . . . . . . . .-55C to +125C VCC Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V VPP Voltages Read . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +12.6 V Program, Erase, and Verify . . . . . . +11.4 V to +12.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
AM28F010
21
MAXIMUM OVERSHOOT
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns
11559H-10
Maximum Negative Input Overshoot
20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V 20 ns 20 ns
11559H-11
Maximum Positive Input Overshoot
20 ns 14.0 V 13.5 V VCC + 0.5 V 20 ns 20 ns
11559H-12
Maximum VPP Overshoot
22
AM28F010
DC CHARACTERISTICS over operating range unless otherwise specified TTL/NMOS Compatible
Parameter Symbol ILI ILO ICCS ICC1 ICC2 ICC3 IPPS IPP1 Parameter Description Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current VCC Programming Current VCC Erase Current VPP Standby Current VPP Read Current Test Conditions VCC = VCC Max, VIN = VCC or VSS VCC = VCC Max, VOUT = VCC or V SS VCC = VCC Max, CE# = VIH VCC = VCC Max, CE# = VIL, OE# = VIH IOUT = 0 mA, at 6 MHz CE = VIL Programming in Progress (Note 4) CE# = VILErasure in Progress (Note 4) VPP = VPPL VPP = VPPH VPP = VPPL VPP = VPPH Programming in Progress (Note 4) VPP = VPPH Erasure in Progress (Note 4) -0.5 2.0 IOL = 5.8 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min A9 = VID A9 = VID Max, VCC = V CC Max 2.4 11.5 5 0.0 11.4 3.2 3.7 13.0 50 VCC +2.0 12.6 10 10 70 0.2 20 20 20 Min Typ Max 1.0 1.0 1.0 30 30 30 1.0 200 1.0 30 30 0.8 VCC + 0.5 0.45 A Unit A A mA mA mA mA A
IPP2 IPP3 VIL VIH VOL VOH1 VID IID VPPL VPPH VLKO
VPP Programming Current VPP Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A9 Auto Select Voltage A9 Auto Select Current VPP during Read-Only Operations VPP during Read/Write Operations Low VCC Lock-out Voltage
mA mA V V V V V A V V V
Note: Erase/Program are inhibited when VPP = VPPL
Notes: 1. Caution: The AM28F010 must not be removed from (or inserted into) a socket when V CC or VPP is applied. If V CC 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 Volts. Also, the AM28F010 has a VPP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = V IH to simulate open outputs. 3. Maximum active power usage is the sum of I CC and IPP. 4. Not 100% tested.
AM28F010
23
DC CHARACTERISTICS CMOS Compatible
Parameter Symbol ILI ILO ICCS ICC1 ICC2 ICC3 IPPS IPP1 IPP2 IPP3 VIL VIH VOL VOH1 VOH2 VID IID VPPL VPPH VLKO A9 Auto Select Voltage A9 Auto Select Current VPPL during Read-Only Operations VPP during Read/Write Operations Low VCC Lock-out Voltage Parameter Description Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current VCC Programming Current VCC Erase Current VPP Standby Current VPP Read Current VPP Programming Current VPP Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 5.8 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min IOH = -100 A, VCC = VCC Min A9 = VID A9 = VID Max, VCC = V CC Max 0.85 VCC VCC -0.4 11.5 5 0.0 11.4 3.2 3.7 13.0 50 VCC + 2.0 12.6 V A V V V Test Conditions VCC = VCC Max, VIN = VCC or VSS VCC = VCC Max, VOUT = VCC or V SS VCC = VCC Max, CE# = VCC + 0.5 V VCC = VCC Max, CE# = V IL, OE# = VIH IOUT = 0 mA, at 6 MHz CE# = VILProgramming in Progress (Note 4) CE# = VILErasure in Progress (Note 4) VPP = VPPL VPP = VPPH VPP = VPPH Programming in Progress (Note 4) VPP = VPPH Erasure in Progress (Note 4) -0.5 0.7 VCC 70 10 10 15 20 20 20 Min Typ Max 1.0 1.0 100 30 30 30 1.0 200 30 30 0.8 VCC + 0.5 0.45 Unit A A A mA mA mA A A mA mA V V V V
Note: Erase/Program are inhibited when VPP = VPPL
Notes: 1. Caution: The AM28F010 must not be removed from (or inserted into) a socket when VCC or VPP is applied. If VCC 1.0 volt, the voltage difference between V PP and VCC should not exceed 10.0 volts. Also, the AM28F010 has a VPP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = V IH to simulate open outputs. 3. Maximum active power usage is the sum of I CC and IPP. 4. Not 100% tested.
24
AM28F010
25
20
ICC Active in mA
15
10 55C 0C 25C 70C 125C
5
0 0 1 2 3 4 5 6 Frequency in MHz 7 8 9 10 11 12
11559G-13
Figure 5. AM28F010--Average ICC Active vs. Frequency VCC = 5.5 V, Addressing Pattern = Minmax Data Pattern = Checkerboar
TEST CONDITIONS
5.0 V
Table 6.
Test Condition
Test Specifications
-70 All others 1 TTL gate 30 10 0.0-3.0 1.5 1.5 0.45-2.4 0.8, 2.0 0.8, 2.0 100 pF ns V V V Unit
Device Under Test CL 6.2 k
2.7 k
Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels
Note: Diodes are IN3064 or equivalent
11559H-14
Output timing measurement reference levels
Figure 6.
Test Setup
AM28F010
25
SWITCHING TEST WAVEFORMS
2.4 V 2.0 V Test Points 0.8 V 0.45 V Input Output 0.8 V 0V Input Output 2.0 V 1.5 V Test Points 1.5 V 3V
AC Testing (all speed options except -70): Inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0". Input pulse rise and fall times are 10 ns.
AC Testing for -70 devices: Inputs are driven at 3.0 V for a logic "1" and 0 V for a logic "0". Input pulse rise and fall times are 10 ns.
11559H-15
SWITCHING CHARACTERISTICS over operating range unless otherwise specified AC Characteristics--Read Only Operation
Parameter Symbols JEDEC tAVAV tELQV tAVQV tGLQV tELQX tEHQZ tGLQX tGHQZ tAXQX tWHGL tVCS Standard Parameter Description tRC tCE tACC tOE tLZ tDF tOLZ tDF tOH Read Cycle Time (Note 2) Chip Enable AccessTime Address Access Time Output Enable Access Time Chip Enable to Output in Low Z (Note 2) Chip Disable to Output in High Z (Note 1) Output Enable to Output in Low Z (Note 2) Output Disable to Output in High Z (Note 2) Output Hold from first of Address, CE#, or OE# Change (Note 2) Write Recovery Time before Read VCC Setup Time to Valid Read (Note 2) Min Max Max Max Min Max Min Max Min Min Min -70 70 70 70 35 0 20 0 20 0 6 50 AM28F010 Speed Options -90 90 90 90 35 0 20 0 20 0 6 50 -120 120 120 120 50 0 30 0 30 0 6 50 -150 150 150 150 55 0 35 0 35 0 6 50 -200 200 200 200 55 0 35 0 35 0 6 50 Unit ns ns ns ns ns ns ns ns ns s s
Notes: 1. Guaranteed by design; not tested. 2. Not 100% tested.
26
AM28F010
AC CHARACTERISTICS--Write/Erase/Program Operations
Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tWHGL tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tVPEL tVCS tVPPR tVPPF tLKO tCS tCH tWP tWPH Standard tWC tAS tAH tDS tDH tWR Description Write Cycle Time (Note 4) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Recovery Time Before Read Read Recovery TIme Before Write CE# Setup TIme CE# Hold TIme Write Pulse Width Write Pulse Width High Duration of Programming Operation (Note 2) Duration of Erase Operation (Note 2) VPP Setup Time to Chip Enable Low (Note 4) VCC Setup Time to Chip Enable Low (Note 4) VPP Rise Time (Note 4) 90% VPPH VPP Fall Time (Note 4) 10% VPPL VCC < VLKO to Reset (Note 4) Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min -70 70 0 45 45 10 6 0 0 0 45 20 10 9.5 100 50 500 500 100 AM28F010 Speed Options -90 90 0 45 45 10 6 0 0 0 45 20 10 9.5 100 50 500 500 100 -120 120 0 50 50 10 6 0 0 0 50 20 10 9.5 100 50 500 500 100 -150 150 0 60 50 10 6 0 0 0 60 20 10 9.5 100 50 500 500 100 -200 200 0 75 50 10 6 0 0 0 60 20 10 9.5 100 50 500 500 100 Unit ns ns ns ns ns s s ns ns ns ns s ms ns s ns ns ns
Notes: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read Only operations. 2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally on the device. 3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing waveform) all set-up, hold and inactive Write-Enable times should be measured relative to the Chip-Enable waveform. 4. Not 100% tested.
AM28F010
27
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
SWITCHING WAVEFORMS
Power-up, Standby Addresses Device and Address Selection Outputs Enabled Data Valid Standby, Power-down
Addresses Stable tAVAV (tRC)
CE# (E#) tEHQZ (tDF) OE# (G#) tWHGL tGHQZ (tDF) tGLQV (tOE) tELQV (t CE) tGLQX (tOLZ) tVCS Data (DQ) tAVQV (tACC) 5.0 V VCC 0V
11559H-16
WE# (W#)
tAXQX (tOH) High Z
High Z
tELQX (tLZ) Output Valid
Figure 7.
AC Waveforms for Read Operations
28
AM28F010
SWITCHING WAVEFORMS
Power-up, Standby Addresses tAVAV (tWC) CE# (E#) tELWL (tCS) OE# (G#) tGHWL (tOES ) WE# (W#) tWLWH (tWP) tDVWH (tDS) Data (DQ) 5.0 V VCC 0V VPPH VPP VPPL
11559G-17
Setup Erase Command
Erase Command
Erasure
Erase-Verify Command
Erase Standby, Verification Power-down
tAVWL (tAS)
tAVAV (tRC) tWLAX (tAH)
tWHEH (t CH) tWHWH2
tEHQZ (tDF)
tWHGL tGHQZ (tDF) tGLQV (tOE) tGLQX (tOLZ) tAXQX (tOH)
DATA IN = A0h
VALID DATA OUT
tWHWL (tWPH) tWHDX (t DH)
DATA IN = 20h DATA IN = 20h
HIGH Z
tVCS tVPEL
tELQX (tLZ) tELQV (t CE)
Figure 8.
AC Waveforms for Erase Operations
AM28F010
29
SWITCHING WAVEFORMS
Power-up, Standby Addresses tAVAV (tWC) tAVWL (t AS) tELWL (tCS) OE# (G#) tGHWL (tOES ) WE# (W#) tWLWH (tWP) tDVWH (tDS) Data (DQ) 5.0 V VCC 0V VPPH VPP VPPL
11559G-18
Setup Program Command
Program Command Latch Address Verify Programming Command and Data
Programming Standby, Verification Power-down
tWLAX (tAH)
tAVAV (tRC)
CE# (E#)
tWHEH (t CH) tWHWH1
tGHQZ (tDF)
tWHGL tGHQZ (tDF) tGLQV (tOE) tGLQX (tOLZ) tAXQX (tOH)
DATA IN = C0h
VALID DATA OUT
t WHWL (t WPH) tWHDX (t DH)
DATA IN = 40h DATA IN
HIGH Z
tVCS tVPEL
tELQX (tLZ) tELQV (t CE)
Figure 9.
AC Waveforms for Programming Operations
30
AM28F010
ERASE AND PROGRAMMING PERFORMANCE
Limits Parameter Chip Erase Time Chip Programming Time Write/Erase Cycles 10,000 Min Typ (Note 1) 1 2 Max (Note 2) 10 12.5 Unit sec sec Cycles Comments Excludes 00h programming prior to erasure Excludes system-level overhead
Notes: 1. 25C, 12 V VPP. 2. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count (Flasherase = 1000 max and Flashrite = 25 max). Typical worst case for program and erase is significantly less than the actual device limit.
LATCHUP CHARACTERISTICS
Parameter Input Voltage with respect to VSS on all pins except I/O pins (Including A9 and VPP) Input Voltage with respect to VSS on all pins I/O pins Current Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. Min -1.0 V -1.0 V -100 mA Max 13.5 V VCC + 1.0 V +100 mA
PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance VPP Input Capacitance VIN = 0 VOUT = 0 VPP = 0 Test Conditions Typ 8 8 8 Max 10 12 12 Unit pF pF pF
Note: Sampled, not 100% tested. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
AM28F010
31
PHYSICAL DIMENSIONS PD032--32-Pin Plastic DIP (measured in inches)
1.640 1.670 32 17 .530 .580 16 .045 .065 .140 .225 .005 MIN 0 10 .630 .700 .009 .015
.600 .625
Pin 1 I.D.
SEATING PLANE .120 .160 .090 .110 .016 .022 .015 .060
16-038-S_AG PD 032 EC75 5-28-97 lv
PL032--32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485 .495 .009 .015 .125 .140 .080 .095 SEATING PLANE .400 REF. .013 .021 .026 .032 TOP VIEW .050 REF. .490 .530 .042 .056
.447 .453
.585 .595 .547 .553
Pin 1 I.D.
SIDE VIEW
16-038FPO-5 PL 032 DA79 6-28-94 ae
32
AM28F010
PHYSICAL DIMENSIONS TS032--32-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95 1.05 Pin 1 I.D. 1
7.90 8.10
0.50 BSC
18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21
0.05 0.15
1.20 MAX 0 5 0.50 0.70
16-038-TSOP-2 TS 032 DA95 3-25-97 lv
AM28F010
33
PHYSICAL DIMENSIONS TSR032--32-Pin Reversed Thin Small Outline Package (measured in millimeters)
0.95 1.05 Pin 1 I.D. 1
7.90 8.10
0.50 BSC
18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21
0.05 0.15
1.20 MAX 0 5 0.50 0.70
16-038-TSOP-2 TSR032 DA95 3-25-97 lv
34
AM28F010
REVISION SUMMARY FOR AM28F010 Revision G+1
Distinctive Characteristics:
AC Characteristics:
Write/Erase/Program Operations: Added the -70 column. Deleted -95 and -250 speed options. Changed speed option in Note 2 to -70.
Switching Test Waveforms: In the 3.0 V waveform caption, changed -95 to -70.
High Performance: The fastest speed option available is now 70 ns.
General Description: Paragraph 2: Changed fastest speed option to 70 ns. Product Selector Guide: Added -70, deleted -95 and -250 speed options. Ordering Information, Standard Products: The -70 speed option is now listed in the example.
Revision H
Matched formatting to other current data sheets.
Revision H+1
Figure 3, Flashrite Programming Algorithm: Moved end of arrow originating from Increment Address box so that it points to the PLSCNT = 0 box, not the Write Program Verify Command box. This is a correction to the diagram on page 6-189 of the 1998 Flash Memory Data Book.
Valid Combinations: Added -70, deleted -95 and -250 combinations.
Operating Ranges:
VCC Supply Voltages: Added -70, deleted -95 and -250 speed options.
AC Characteristics:
Revision H+2
Programming In A PROM Programmer: Deleted the paragraph "(Refer to the AUTO SELECT paragraph in the ERASE, PROGRAM, and READ MODE section for programming the Flash memory device in-system)."
Read Only Operations Characteristics: Added the -70 column and test conditions.
Deleted -95 and -250 speed options.
Trademarks
Copyright (c) 1998 Advanced Micro Devices, Inc. All rights reserved. ExpressFlash is a trademark of Advanced Micro Devices, Inc. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
AM28F010
35

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